Awards

In this paper, we present a novel, deep-learning framework based on a Convolutional Neural Network model for predicting the routability of a placement. We also incorporate the deep-learning model into a state-of-the-art placement tool, and show how the model can be used to (1) avoid costly, but futile, place-and-route iterations, and (2) improve the placer's ability to produce routable placements for hard-to-route circuits using feedback based on routability estimates generated by the proposed model. The model is trained and evaluated using over 26K placement images derived from 372 benchmarks supplied by Xilinx Inc. Experimental results show that the proposed framework achieves a routability prediction accuracy of 97%, while exhibiting runtimes of only a few milliseconds.

First prize for the paper "An Effective FPGA Placement Flow Selection Framework using Machine Learning"

The paper shows how machine learning can be used to accurately and efficiently identify regions of congestion during placement of circuit components on FPGA devices. Placement tools that fail to optimize for congestion often fail to produce a feasible solution in the subsequent routing stage. The proposed machine learning model is as accurate as state-of-the-art global routers, but runs 291x faster, thus allowing congestion estimation to be performed more frequently during placement compared with other congestion estimation techniques.

The Guelph FPGA CAD group finished 3rd at the 2016 International Symposium on Physical Design (ISPD) FPGA Routability-Driven Placement Contest.

The Guelph FPGA CAD group finished 5th at the 2017 International Symposium on Physical Design (ISPD) FPGA Clock-Aware Placement Contest.

The Guelph FPGA CAD group won the best-paper award at the 24th Reconfigurable Architectures Workshop, May 29-30, Orlando, Florida, USA, 2017.