1st Runtime-First FPGA Interchange Routing Contest, 32nd International Symposium on Field-Programmable Gate Arrays (ISFPGA), March 3-5, 2024, Monterey, CA
The Guelph FPGA CAD group won 1st place in the FPGA Routing Contest at the 2024 International Symposium on Field-Programmable Gate Arrays (ISFPGA), presented in Monterey, California, on March 4, 2024.
Best Paper Best Track Paper on Track EDA/CAD, Test and Reliability, SBCCI 2022 ("Chip in the Minuano"), Virtually in Brazil, August 22-26, 2022
The Guelph FPGA CAD group won a Best Paper award in the EDA/CAD, Test and Reliability track of SBCCI 2022 for their paper "Integrating Machine-Learning Probes into the VTR FPGA Design Flow", at the 2022 SBCCI forum hosted virtually in Rio Grande do Sul, Brazil.
Best Paper 29th International Conference on Field Programmable Logic and Applications (FPL), September 8 — 12, 2019,
In this paper, which won the Best Paper award at FPL 2019 in Barcelona, Spain, we present a novel, deep-learning framework based on a Convolutional Neural Network model for predicting the routability of a placement. We also incorporate the deep-learning model into a state-of-the-art placement tool, and show how the model can be used to (1) avoid costly, but futile, place-and-route iterations, and (2) improve the placer's ability to produce routable placements for hard-to-route circuits using feedback based on routability estimates generated by the proposed model. The model is trained and evaluated using over 26K placement images derived from 372 benchmarks supplied by Xilinx Inc. Experimental results show that the proposed framework achieves a routability prediction accuracy of 97%, while exhibiting runtimes of only a few milliseconds.
Best Paper The 30th International Conference on Microelectronics (ICM2018), December 16 – 19, 2018, Sousse, Tunisia
First prize for the paper "An Effective FPGA Placement Flow Selection Framework using Machine Learning"
Best Paper 2018 Michal Servit Award at the 28th International Conference on Field Programmable Logic and Applications (FPL), August 27 – 31, Dublin, Ireland
The paper shows how machine learning can be used to accurately and efficiently identify regions of congestion during placement of circuit components on FPGA devices. Placement tools that fail to optimize for congestion often fail to produce a feasible solution in the subsequent routing stage. The proposed machine learning model is as accurate as state-of-the-art global routers, but runs 291x faster, thus allowing congestion estimation to be performed more frequently during placement compared with other congestion estimation techniques.
3rd 2016 ACM International Symposium on Physical Design FPGA Placement Contest
The Guelph FPGA CAD group finished 3rd at the 2016 International Symposium on Physical Design (ISPD) FPGA Routability-Driven Placement Contest.
5th 2017 International Symposium on Physical Design (ISPD) FPGA Clock-Aware Placement Contest
The Guelph FPGA CAD group finished 5th at the 2017 International Symposium on Physical Design (ISPD) FPGA Clock-Aware Placement Contest.
Best Paper 2017 Reconfigurable Architectures Workshop
The Guelph FPGA CAD group won the best-paper award at the 24th Reconfigurable Architectures Workshop, May 29-30, Orlando, Florida, USA, 2017.