Guelph FPGA CAD Group's winning submission for the ISFPGA 2024 Runtime-First FPGA Interchange Routing Contest, sponsored by AMD/Xilinx. This presentation introduces a multi-threaded routing algorithm for Xilinx FPGA devices, which is designed to leverage high-thread-count CPUs to achieve substantial improvements in runtime. Using a two-phase routing architecture and various optimization to scheduling and data structures, the team were able to see an improvement of up to 7x on runtime when compared to the RWRoute baseline.
Presentation in Toronto on September 20th, 2018. In this talk, we introduce a new, analytic routability-aware placement algorithm for Xilinx UltraScale FPGA architectures. The proposed algorithm, called GPlace3.0, seeks to optimize both wirelength and routability. Our work contains several unique features including a novel window-based procedure for satisfying legality constraints in lieu of packing, an accurate congestion estimation method based on modifications to the pathfinder global router, and a novel detailed placement algorithm that optimizes both wirelength and external pin count.
In this talk given at the FPGA Seminar series hosted by the University of Toronto, and supported by Intel/Altera and Xilinx, we propose a novel algorithm for parallel placement, based on simulated annealing, where the amount of parallel work directly scales with the size of the net-list to be placed.
In this talk given at the FPGA Seminar series hosted by the University of Toronto, and supported by Intel/Altera and Xilinx, we propose a novel algorithm for parallel placement, based on analytic placement, based on parallel patters with well-defined iso-efficiency functions.